Synchronizers or asynchronous links can be employed in order to cross clock boundaries in a chip with multiple clock domains.
Asynchronous circular FIFOs are generally used to guarantee high performance in terms of frequency and bandwidth. Such a kind of FIFO relies on the idea to write data in one clock domain and read them in a safe way in the other domain. The main idea is to synchronize the information about the pointers used to address the FIFO. These pointers are generated in one clock domain and latched in the other one. To avoid a wrong sampling of the pointer vector due to different wire delay of its bits, the pointer is usually Gray coded.
The synchronization techniques force to place together in the same physical cluster the Gray pointer generation logic clocked by the write clock domain, and the synchronization module, clocked by the receiving clock. This is done primarily to avoid large differences between the delays of the wires crossing the clock boundary. This also implies that the two clock domains have to be contiguous. As a consequence, clock domains generally have to span large regions of the chip respecting the maximum clock skew permitted by the clock tree. The balancing required on the clock tree to ensure the same phase in “remote” zones on the chip is a heavy task in Deep Sub-micron (DSM) technologies, and back-end teams have to spend a lot of time and effort to face the problem of the timing closure.
Current solutions to solve this issue are based either on this time consuming, difficult and not always possible task, or on using a different, safer 4-phases asynchronous communication. When the number of different clock domains increases, due to a large amount of IPs being present in the SoC, this first solution is no longer feasible, while the asynchronous approach based on 4-phases signaling protocol, introducing a heavy bandwidth limitation, does not permit to meet high performance requirements.
The problem in using synchronizers is that clock signals have to be distributed and balanced. Asynchronous links enable to overcome the above problem, but suffer from other serious problems: limited bandwidth, wire-overhead and complexity (area overhead).
European Patent Application No. 06291440 discloses a synchronization system for synchronizing modules in an integrated circuit including a so-called SKew Insensitive Link (SKIL) to implement a mesochronous mechanism (see also D. Mangano, et al.: “Skew Insensitive Physical Links for Network on Chip”, 1st International Conference on Nano-Networks (NANO-NET 2006), Lausanne, Switzerland, 14-16 Sep. 2006).
As is well known, the term “mesochronous” denotes a relationship between two signals such that their corresponding significant instants occur at the same average rate. A mesochronous network is thus a network where the clocks run with the same frequency but unknown relative phases.
Additionally, European Patent Application No. 07108878 discloses a full-duplex mesochronous link.